Alternate Register Mapping

ABSTRACT

A novel method of providing alternate access to a storage element for holding a data element in a network interface. The storage element is accessed via a first access path when the network interface operates with a first type of software, and via a second access path when a second type of software is used. The first access path is allocated in response to a first address signal identifying a first register required by the first type of software to hold the data element. The second access path is allocated in response to a second address signal identifying a second register required by the second type of software to hold the data element.

RELATED APPLICATIONS

This application claims priority from U.S. Provisional PatentApplication No. 60/169,271, filed Dec. 7, 1999, which is incorporatedherein by reference.

FIELD OF THE INVENTION

The present invention relates to data processing, and more particularly,to method and system for providing alternate access to the same storageelement in a register block.

BACKGROUND ART

The growth in computer applications that require heavy data traffic andthe increasing availability of high-speed transmission lines andintelligent communication switches create a need for data communicationnetworks able to manage a huge amount of data at high rates. Complexsoftware that addresses high-performance requirements of data networksis used to manage communications between a CPU and network devices.

Such software may require that certain bits in a network device, such ascontrol and status bits, be accessed in a specific way. For example, aparticular bit is required to be located in a specific position in aparticular register along with some other bits accessible during thesame access operation or sequence of access operations.

Thus, to be able to operate with different types of software, a networkdevice should store the same information in various registers. Separatecontrol means should be provided to maintain consistency of bitscorresponding to the same information.

Therefore, it would be desirable to enable a network device to operatewith different types of software without storing the same information indifferent locations.

DISCLOSURE OF THE INVENTION

The present invention offers a novel method of providing alternateaccess to a storage element for holding a data element in a dataprocessing system. In accordance with this method, the storage elementis accessed via a first access path when a first type of software isused to operate a data processing system, and the storage element isaccessed via a second access path when a second type of software isused.

In a preferred embodiment, the first access path may be allocated inresponse to a first address signal identifying a first register requiredby the first type of software to hold the data element. The secondaccess path may be allocated in response to a second address signalidentifying a second register required by the second type of software tohold the data element.

In accordance with a first aspect of the invention, the data processingsystem operable with at least two types of software comprises a hostinterface for providing address, data and control signals from a host,and a storage element for holding data accessible via the hostinterface. Alternate access circuitry is configured for providing accessto the storage element so as to access the data as a first data elementin the first register when the system operates with the first type ofsoftware, and as a second data element in the second register when thesystem operates with the second type of software.

In particular, the alternate access circuitry may be configured toperform writing data into the storage element in response to the firstaddress signal supplied from the host interface to access the firstregister, and in response to the second address signal supplied from thehost interface to access the second register.

Also, the alternate access circuitry may be configured to performreading data from the storage element in response to the first addresssignal supplied from the host interface to access the first register,and in response to the second address signal supplied from the hostinterface to access the second register.

In accordance with a preferred embodiment of the invention, thealternate access circuitry may comprise a writing mutiplexer having afirst input for supplying a first data element to the storage elementwhen the system operates with the first type of software, and a secondinput for supplying a second data element to the storage element whenthe system operates with the second type of software. When a firstselect signal is asserted, the writing multiplexer passes the first dataelement to the storage element. When a second select signal is asserted,the writing multiplexer passes the second data element to the storageelement. While the first select signal is asserted in response to thefirst address signal, the second select signal is asserted in responseto the second address signal.

Also, the alternate access circuitry may comprise a first reading gatecoupled to the storage element for outputting a first data element whenthe system operates with the first type of software, and a secondreading gate coupled to the storage element for outputting a second dataelement when the system operates with the second type of software. Thefirst reading gate may be configured to output the first data element inresponse to the first address signal, and the second reading gate may beconfigured to output the second data element in response to the secondaddress signal.

In accordance with another aspect of the present invention, a networkinterface having a host interface and a storage element for holding adata element accessible via the host interface, is provided withalternate access circuitry coupled to the storage element for providingmultiple paths for accessing the data element.

The alternate access circuitry may be configured to select a path foraccessing the data element depending on a type of software used tooperate the network interface. In particular, the pass for accessing thedata element is allocated in response to an address signal supplied fromthe network interface to access a predetermined register, when thenetwork interface operates with a selected type of software thatrequires the data element to be held in the predetermined register.

Still other objects and advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description, wherein only the preferred embodiment of theinvention is shown and described, simply by way of illustration of thebest mode contemplated of carrying out the invention. As will berealized, the invention is capable of other and different embodiments,and its several details are capable of modifications in various obviousrespects, all without departing from the invention. Accordingly, thedrawings and description are to be regarded as illustrative in nature,and not as restrictive.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of an exemplary network interface, in whichthe present invention may be implemented.

FIG. 2 is a block-diagram illustrating a register access scheme in thenetwork interface.

FIG. 3 is a diagram of alternate register access circuitry of thepresent invention.

BEST MODE FOR CARRYING-OUT THE INVENTION

Although the invention has general applicability in the field of dataprocessing, the best mode for practicing the invention is based in parton the realization of a network interface in a packet switched network,such as an Ethernet (IEEE 802.3) network.

FIG. 1 is a block diagram of an exemplary network interface 10 thataccesses the media of an Ethernet network according to an embodiment ofthe present invention.

The network interface 10, preferably a single-chip, 32-bit Ethernetcontroller, provides an interface between a local bus 12 of a computer,for example, a peripheral component interconnect (PCI) local bus, and anEthernet-based media 50. The reference numeral 50 identifies either anactual network medium, or alternately a signal path (e.g., a mediaindependent interface (MII)) to a physical layer transceiver coupled tothe network media.

The network interface 10 includes a PCI bus interface unit 16, a memorycontrol unit 18, a network interface portion 20, a descriptor managementunit 22 and a register control and status unit 24. The network interfaceportion 20 includes an IEEE 802.3 compliant and full-duplex capablemedia access control (MAC) core 26, a Media Independent Interface (MII)port 28 for connecting external 10Mb/s, 100 Mb/s or 1000 Mb/stransceivers, an External Address Detection Interface (EADI) port 30,and a network port manager unit 32. The network interface 10 alsoincludes an EEPROM interface 34 for reading from and writing to anexternal EEPROM, an LED control 36, an IEEE 1149.1-compliant JTAGBoundary Scan test access port interface 38, a clock generation unit 40,and an expansion bus interface 42. The expansion bus interface unit 42interfaces to an external or internal data memory (not shown in FIG. 1)for frame storage and also to non-volatile (e.g., EPROM or Flash memory)storage for boot ROM use during startup.

The PCI bus interface unit 16, compliant with the PCI local busspecification (revision 2.2), receives data frames from a host computermemory via the PCI bus 12. The PCI bus interface unit 16, under thecontrol of the descriptor management unit 22, receives transfers fromthe host computer via the PCI bus 12. For example, transmit datareceived from the PCI bus interface unit 16 is passed to the memorycontrol unit 18 which stores it in the data memory. Subsequently, thememory control unit 18 retrieves the transmit data from the data memoryand passes it to the MAC 26 for eventual transmission to the network.Similarly, receive data from the network 50 is processed by the MAC 26and passed to the memory control unit 18 for storage in the data memory.Subsequently, the memory control unit 18 retrieves the receive data fromthe data memory and passes it to the PCI bus interface unit 16 fortransfer to the host computer via the PCI bus 12.

The descriptor management unit 22 manages the transfers of data to andfrom the host computer via the PCI bus interface unit 16. Datastructures contained in the memory of the host computer specify the sizeand location of data buffers along with various control and statusinformation. The descriptor management unit 22 interfaces with thememory control unit 18 to insert control information into the transmitdata stream and to retrieve status information from the receive datastream.

The network interface portion 20 includes a network port manager 32 thatperforms auto-negotiation functions by communicating via the media 50with a corresponding auto-negotiation unit in the link partner (e.g., acentralized hub, repeater, workstation, or switch).

The network interface 10 also includes a power management unit 44 thatenables remote activation (i.e., turn-on) of the host computer via thenetwork medium 50 by detecting a predetermined pattern on the networkmedium 50 according to Microsoft OnNow and ACPI specifications,including compliance with Magic Packet technology and PCI Bus PowerManagement Interface Specification protocols.

The network interface 10 also includes a MIB counter unit 46 whichaccepts information from the MAC 26 regarding frame transmission andreception and maintains the statistics necessary for network management.These statistics are accessed by the host computer via the PCI businterface unit 16.

In accordance with the present invention, the network interface 10 isenabled to operate with different types of software. Each software typemay request that certain bits in registers of the network interface 10,such as control and status bits, be accessed in a specific way. Forexample, a particular bit is required to be located in a specificposition in a particular register along with some other bits accessibleduring the same access operation or sequence of access operations. Thepresent invention allows the network interface 10 to avoid storing thesame information in different registers. Instead, the invention providestwo or more ways of accessing certain bits stored in registers of thenetwork interface 10.

As a result, each bit is stored only in a single storage element or aregister location. However, alternate accesses are provided to thisstorage element, depending on the software being employed.

Referring to FIG. 2, the network interface 10 comprises a register logicblock 100 that manages top-level registers of the network interface 10.The register logic block 100 is coupled to the PCI bus interface unit 16via a register interface 102 to allow read and write accesses to theregisters. The PCI bus interface 16 recognizes PCI read and writeaccesses to the registers, and sends register address signal and writeand read signals to the register logic block 100. The register addresssignal identifies a register being accessed from the PCI bus 12. Thewrite and read signals identify whether a write or read access operationis being performed. Data being written or read to or from the accessedregister is transferred via a data bus in the register interface 102.

For example, the register logic block 100 may include a decoder andmultiple global registers such as control and status registers, andinterrupt registers. The decoder decodes the address of the registerbeing accessed via the PCI bus interface unit 16, and provides access tothe selected register. The control and status registers may comprisecontrol bits for controlling some functions of the network interface 10such as switching into a particular mode of operation, the start or stopof frame transmission or reception, and status bits for indicating thestatus of certain network interface operations. The interrupt registersmay comprise interrupt bits corresponding to various transmit andreceive interrupt events. Among transmit interrupt events are transmitdescriptor interrupts asserted when a transmit descriptor has beenprocessed, free bytes interrupts asserted when a certain number of bytesbecome free in the transmit buffer 32 a, transmit frame completeinterrupts indicating that a transmit frame has been either successfullytransmitted to the network or aborted due to error conditions, etc.Receive interrupt events include receive frame complete interruptsindicating that an entire receive frame is processed, receiveout-of-descriptor interrupts asserted when the network adapter wants totransfer receive data to the system memory but no receive descriptor isavailable, etc. The interrupt bits are sent to the PCI bus interfaceunit 16 for activating the interrupt request output INTA/.

In accordance with a disclosed embodiment of the present invention, theregister logic block 100 comprises alternate register access circuitry110 for providing alternate access to certain bits stored in registersof the register logic block 100. FIG. 3 illustrates an exemplaryalternate register access circuitry 110 for providing read and writeaccesses to a storage element 120, such as a flip-flop, that holds thevalue of a control bit F1. The control bit F1 may be a bit set orcleared by a PCI write access, and used to control some function withinthe network interface 10. For example, the control bit F1 may be set toinstruct the network interface 10 to switch into a particular mode ofoperation, to start or stop frame transmission or reception, etc.

As illustrated in FIG. 3, the storage element 120 for holding the bit F1can be accessed in two different ways. First, it can be accessed as abit arranged in a first register such as register 3, in a first bitposition, for example, position 1 of the register 3. Also, this storageelement can be accessed as a bit arranged in a second register such asregister 8, in a second bit position, for example, position 5 of theregister 8. As a result, the bit F1 can be written or read to or from asingle storage element when the network interface 10 is controlled by afirst type of software that requires this bit to be in the firstregister, and when the network interface 10 is controlled by a secondtype of software that requires the bit F1 to be arranged in the secondregister.

The exemplary alternate register access circuitry 110 shown in FIG. 3comprises a writing multiplexer 122 having inputs 0, 1 and 2. Datasignals DATA[1] and DATA[5] representing data to be written into thestorage element 120 are supplied to the inputs 1 and 2, respectively.

The DATA[1] signal represents data being written or read to or from thestorage element 120 when the network interface 10 is operated by a firsttype of software. The DATA[5] signal represents data being written orread to or from the storage element 120 when the network interface 10 isoperated by a second type of software. The input 3 is coupled to thestorage element 120.

The multiplexer 122 is controlled by controlled signals SEL0, SEL1 andSEL2 respectively asserted to connect the inputs 0, 1 and 2 to theoutput of the multiplexer 122. The control signal SEL0 is produced atthe output of an AND gate 124 supplied with the control signals SEL1 andSEL2 respectively inverted by inverters 126 and 128.

The control signal SEL1 is produced at the output of an AND gate 130supplied with the write signal and the register address signalidentifying access to the register 3. The control signal SEL2 isproduced at the output of an AND gate 132 supplied with the write signaland the register address signal identifying access to the register 8.The output of the multiplexer 122 is coupled to the storage element 120via a D flip-flop 134 provided to synchronize writing access operations.

When the network interface 20 is controlled by the first type ofsoftware to write data into the memory element 120, a register addresssignal identifying the register 3, together with the write signal, issupplied to the register logic block 100. As a result, the controlsignal SEL1 is asserted to pass the DATA[1] signal to the output of themultiplexer 122. Thus, the control bit F1 is written as a bit in bitposition 1 of the register 3.

When the network interface 20 is controlled by the second type ofsoftware to write data into the memory element 120, a register addresssignal identifying the register 8, together with the write signal, issupplied to the register logic block 100. As a result, the controlsignal SEL2 is asserted to pass the DATA[5] signal to the output of themultiplexer 122. Thus, the control bit F1 is written as a bit in bitposition 5 of the register 8.

If no access is performed to write the F1 bit, the control signal SEL0is asserted to maintain the current value in the storage element 120.

Further, the exemplary alternate register access circuitry 110 comprisesfirst and second reading gates 134 and 136 connected to the storageelement 120 for outputting the DATA[1] and DATA[5] signals,respectively. The gates 134 and 136 are controlled by first and secondread control signals produced at outputs of AND gates 138 and 140,respectively.

The AND gate 138 is supplied with the read signal and the registeraddress signal identifying register 3, when the network interface 10 iscontrolled by the first type of software to read the control bit F1. TheAND gate 140 is supplied with the read signal and the register addresssignal identifying register 5, when the network interface 10 iscontrolled by the second type of software to read the control bit F1.

Thus, when the network interface 10 operates with the first type ofsoftware, a read access operation to bit position 1 of the register 3results in reading the control bit F1 from the storage element 120 asthe DATA[5] signal. Similarly, when the network interface 10 operateswith the second type of software, a read access operation to bitposition 5 of the register 8 results in reading the control bit F1 fromthe storage element 120 as the DATA[1] signal.

Accordingly, the present invention enables the network interface 10 tooperate with different types of software without storing the sameinformation in different locations. Instead, a particular bit accessiblevia the PCI bus is stored in a single storage element. Alternateregister access circuitry provides alternate circuits for accessing thisstorage element. When the network interface operates with a first typeof software, the storage element is being accessed as a first positionof a first register. However, when the network interface operates with asecond type of software, the storage element is being accessed as asecond position of a second register.

Those skilled in the art will recognize that the present inventionadmits of a number of modifications, within the spirit and scope of theinventive concepts. For example, the alternate register access circuitrymay be implemented in a number of different ways.

While the foregoing has described what are considered to be preferredembodiments of the invention it is understood that various modificationsmay be made therein and that the invention may be implemented in variousforms and embodiments, and that it may be applied in numerousapplications, only some of which have been described herein. It isintended by the following claims to claim all such modifications andvariations which fall within the true scope of the invention.

1. A data processing system operable with at least two types ofsoftware, the system comprising: a host interface for providing address,data and control signals from a host, a storage element for holding dataaccessible via the host interface, and alternate access circuitry forproviding access to the storage element so as to access the data as afirst data element in a first register when the system operates with afirst type of software, and as a second data element in a secondregister when the system operates with a second type of software.
 2. Thesystem of claim 1, wherein the alternate access circuitry is configuredto perform writing data into the storage element in response to a firstaddress signal supplied from the host interface to access the firstregister, when the system operates with the first type of software. 3.The system of claim 2, wherein the alternate access circuitry isconfigured to perform writing data into the storage element in responseto a second address signal supplied from the host interface to accessthe second register, when the system operates with the second type ofsoftware.
 4. The system of claim 1, wherein the alternate accesscircuitry is configured to perform reading data from the storage elementin response to a first address signal supplied from the host interfaceto access the first register, when the system operates with the firsttype of software.
 5. The system of claim 4, wherein the alternate accesscircuitry is configured to perform reading data from the storage elementin response to a second address signal supplied from the host interfaceto access the second register, when the system operates with the secondtype of software.
 6. The system of claim 1, wherein the alternate accesscircuitry comprises a writing multiplexer having a first input forsupplying the first data element to the storage element when the systemoperates with the first type of software, and a second input forsupplying the second data element to the storage element when the systemoperates with the second type of software.
 7. The system of claim 6,wherein the writing multiplexer is controlled by a first select signalto pass the first data element to the storage element when the firstselect signal is asserted.
 8. The system of claim 7, wherein the writingmultiplexer is controlled by a second select signal to pass the seconddata element to the storage element when the second select signal isasserted.
 9. The system of claim 8, wherein the first select signal isasserted in response to a first address signal supplied from the hostinterface to access the first register.
 10. The system of claim 9,wherein the second select signal is asserted in response to a secondaddress signal supplied from the host interface to access the secondregister.
 11. The system of claim 1, wherein the alternate accesscircuitry comprises a first reading gate coupled to the storage elementfor outputting the first data element when the system operates with thefirst type of software, and a second reading gate coupled to the storageelement for outputting the second data element when the system operateswith the second type of software.
 12. The system of claim 11, whereinthe first reading gate is configured to output the first data element inresponse to a first address signal supplied from the host interface toaccess the first register.
 13. The system of claim 12, wherein thesecond reading gate is configured to output the second data element inresponse to a second address signal supplied from the host interface toaccess the second register.
 14. A network interface comprising: a hostinterface for supplying address, data and control signals from a host, astorage element for holding a data element accessible via the hostinterface, and alternate access circuitry coupled to the storage elementfor providing multiple paths for accessing the data element, andconfigured to select a first path for accessing the data element in afirst register when a first type of software is used to operate thenetwork interface, and to select a second path for accessing the dataelement in a second register when a second type of software is used tooperate the network interface.
 15. The network interface of claim 14,wherein the path for accessing the data element is allocated in responseto an address signal supplied from the network interface to access apredetermined register, when a selected type of software is used tooperate the network interface.
 16. The network interface of claim 15,wherein the selected type of software requires the data element to beheld in the predetermined register.
 17. In a data processing system, amethod of providing access to a storage element for holding a dataelement, comprising the steps of: accessing the data element via a firstaccess path when a first type of software is used to operate the dataprocessing system, and accessing the data element via a second accesspath when a second type of software is used to operate the dataprocessing system.
 18. The method of claim 17, wherein the first accesspath is allocated in response to a first address signal identifying afirst register required by the first type of software to hold the dataelement.
 19. The method of claim 18, wherein the second access path isallocated in response to a second address signal identifying a secondregister required by the second type of software to hold the dataelement.